램리스 x86 클래스 프로세서를 실행할 수 있습니까?

최신 x86 프로세서에는 512K 이상의 L2 캐시가 있습니다. 이 양의 메모리에 완전히 맞는 응용 프로그램이 있습니다. RAM이 부착되지 않은 상태에서 이러한 칩을 실행할 수 있습니까? 그렇다면 CPU가 RAM 일관성을 유지하려고 할 때 라이트 백 타이밍 페널티를 없애는 방법이 있습니까?

특정 응용 프로그램을 염두에 두지 않고 유휴 호기심입니다. 나는 어딘가에 이것이 유용 할 틈새 응용 프로그램이 있다고 확신합니다.

memory cpu ram

— 마크 랜섬
소스

답변:

그래 넌 할수있어. 존재하지 않는 연속적인 실제 메모리 위치에서 읽기를 수행하여 캐시에 태그를 설정합니다. 그런 다음 캐시 라인의 추가 채우기를 끄고 쓰기 저장을 입력하여 캐시에 대한 읽기 / 쓰기를 제한하면 일반 RAM처럼 작동합니다.

Some of the bios-replacement projects do this because then you can spend much more code on the chipset and chipset memory controller setup, so you can write it in C for example.

This practice is widely used for embedded-class CPUs as well for handling bootloaders. The methods to turn the cache into a RAM-like mode vary a bit.

For a brief low-level introduction you can check out this presentation.

Note that as others have pointed out you still need to load the boot-code from somewhere obviously.

— Bjorn Wesen
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In fact, I think pretty much all modern BIOSes use this and pretty much all modern x86 CPUs has official support for it for that reason.

— Yuhong Bao

When the CPU comes out of reset, cache is turned off. The BIOS is what initially configures and clears out the cache. So no, you can't run it RAM-less because there is no RAM to boot the thing up in the first place.

Couldn't the first few instructions from ROM initialize and turn on the cache, without using RAM?

— Mark Ransom

@Mark Ransom Modern Intel processors (and many other CPU's) use Serial Flash to store the BIOS. But it cannot execute code from serial flash. Instead the CPU copies this serial flash to RAM and then executes it.

Hah, my ignorance is showing - you can see how many years it's been since I've done hardware design. So the CPU copies the flash automatically before the first instruction is executed? That would be a nasty chicken/egg problem to overcome.

— Mark Ransom

@David Strictly speaking it's not 'serial' flash but 'Firmware Hub'. This differs from 'serial' in that it transfers 4 bits at a time instead of 1.

— Majenko

@Mark Ransom There are many CPU's/MCU's/DSP's that will boot over a serial link (Serial Flash, RS-232, SPI, etc.). They all accomplish this by having a small ROM inside the CPU that it boots from, and that code will load the "real" code from wherever. Running a RAM-Less system could, in theory, be possible by having Intel modify this code to use the cache instead of external RAM. But I doubt Intel will do this.

I don't know how accurate this is, but these are my thoughts:

I don't think there is any way you can get programmatic access to the cache. You cannot guarantee from one instruction to the next what would be in the cache, and where it would be located, so you cannot use it reliably as RAM even if you could access it directly.

You could run an x86 without RAM, but you wouldn't be able to get it to do very much useful. You'd be restricted to purely using the internal registers for data storage.

— Majenko
소스

The cacheline fill and flush protocols are thoroughly documented and configurable in most CPUs including the x86. Cacheline contents is not flushed in a random way between instructions. See my answer on how you typically set it up to behave as linear RAM.

— Bjorn Wesen

I've written a hex loader utility for an 80x86 clone which would work correctly without any RAM; IIRC, I implemented a one-level call stack using SP to hold return address. Since the ROM was on the same bus as the RAM, it wasn't terribly likely that there'd be a problem that would let the ROM work when the RAM didn't, but in such a case the loader could diagnose the problem. On some other micros with external code buses but a small amount of internal code space, being able to run code on a system with a broken bus was a useful diagnostic tool.

— supercat

@I could be mistaken but is RAM not for binary code and for read and writes by the processor ?

— Victor Mehta